As semiconductor devices have become more highly integrated, a number of metal wirings may be increased. In addition, a pitch of the metal wirings may be reduced. Due to a pitch reduction of the metal wirings, a resistance of the metal wirings may be increased. An interlayer dielectric may insulate the metal wirings from each other. Metal wirings may produce parasitic capacitance, which may have a detrimental effect on a semiconductor device. That is, an RC constant that may determine a response speed of a semiconductor device and power consumption may be increased.
There may be a need for an interlayer dielectric having a low dielectric constant that may be suitable for highly integrated semiconductor devices. In some instances, instead of using an un-doped silica glass (USG), a fluorine silicate glass (FSG) may be used as the interlayer dielectric having a low dielectric constant.
Although fluorine system film may have excellent gap-fill characteristics, a difference of film thickness between highly integrated patterns and non-highly integrated pattern has increased.
FIGS. 1 and 2 are example diagrams illustrating a related art method for forming an interlayer dielectric of a semiconductor.
Scribe lane region 1, which may be a photo key region for an interlayer mutual connection, and a main chip 2 are illustrated in FIG. 1.
Referring to FIG. 1, an oxide may be deposited on first metal M1, for example by chemical vapor deposition (CVD) First interlayer dielectric 20 may thus be formed. Chemical mechanical polishing (CMP), for example via photolithography, and via etch processes may be sequentially performed, and may form a via hole.
The via hole may be filled, for example with a tungsten W 10, and may form a via electrode. Second metal M2 may be patterned, for example on the via hole.
Shallowing of metal lines in a sidewall may occur if a step coverage characteristic deteriorates during a metal physical vapor deposition PVD, and may cause a high resistance and electromigration in a surface planarized by the CMP.
During a photolithography process for forming the via hole, due to an oxide step coverage of a first interlayer dielectric in a photo key and overlay pattern present at a main chip region 2 and a scribe lane region 1, a defocus may occur during the via photolithography process. Accordingly, as illustrated in main chip region 2 of FIG. 1, an opening of a via hole, may not be completed.
Referring to FIG. 2, an oxide may be deposited on second metal M2, for example by a CVD, and may form second interlayer dielectric 21. A planarization process may be carried out by the CMP. A via hole may then be formed by via photolithography/etch processes.
The via hole may be filled with tungsten 11, and a third metal M3 may be formed. As the interlayer dielectric is increased, a via photolithography defocus may become significant due to an increase in a step coverage difference in the photo key and overlay pattern present at the scribe lane region 1 and the main chip region 2.
FIG. 3 is a SEM photograph showing a via that is not open due to a step coverage. As described above, in the CMP process being performing after a formation of the interlayer dielectric, as the step coverage characteristic deteriorates, a defocus may arise during a formation of the via hole. This may reduce a yield of semiconductor devices.